Semiconductor devices and methods of fabrication

ABSTRACT

Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.

BACKGROUND

With the development of the semiconductor industry, three-dimensional(3D) semiconductor devices are widely explored. However, the structuresof the 3D semiconductor devices that include stacked tiers (e.g.,layers) and vertical channels extending into the stacked tiers, as wellas the techniques of making such 3D semiconductor devices, may presentsome implementation challenges.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1N are cross-sectional views illustrating an example method ofmaking a 3D semiconductor device, in which each figure illustrates arepresentative stage of forming the device, according to an embodimentof the application.

FIGS. 2A-2H are cross-sectional views illustrating an example method ofmaking a 3D semiconductor device, in which each figure illustrates arepresentative stage of forming the device, according to anotherembodiment of the application.

FIG. 3 is a flow chart illustrating a method of making a 3Dsemiconductor device according to an embodiment of the application.

FIGS. 4A-4H are cross-sectional views illustrating an example method ofmaking a 3D semiconductor device, in which each figure illustrates arepresentative stage of forming the device, according to anotherembodiment of the application.

DETAILED DESCRIPTION

In the following detailed description of the embodiments, reference ismade to the accompanying drawings which form a part hereof, and in whichis shown by way of illustration specific illustrative embodiments inwhich some embodiments of the invention may be practiced.

Recently, 3D semiconductor devices (e.g., 3D NAND memory devices) havecome into use due to severe scaling challenges. However, 3Dsemiconductor devices that include stacked tiers and channels extendinginto the stacked tiers impose structural and manufacturing challenges.For example, in 3D semiconductor devices, interfaces may exist insidechannels that extend into stacked tiers.

The term “horizontal” as used in this document is defined as a planeparallel to the conventional plane or surface of a substrate, such asthat underlying a wafer or die, regardless of the actual orientation ofthe substrate at any point in time. The term “vertical” refers to adirection perpendicular to the horizontal as defined above.Prepositions, such as “on,” “over,” and “under” are defined with respectto the conventional plane or surface being on the top or exposed surfaceof the substrate, regardless of the orientation of the substrate; andwhile “on” is intended to suggest a direct contact of one structurerelative to another structure which it lies “on”(in the absence of anexpress indication to the contrary); the terms “over” and “under” areexpressly intended to identify a relative placement of structures (orlayers, features, etc.), which expressly includes—but is not limitedto—direct contact between the identified structures unless specificallyidentified as such. Similarly, the terms “over” and “under” are notlimited to horizontal orientations, as a structure may be “over” areferenced structure if it is, at some point in time, an outermostportion of the construction under discussion, even if such structureextends vertically relative to the referenced structure, rather than ina horizontal orientation.

The terms “wafer” and “substrate” are used herein to refer generally toany structure on which integrated circuits are formed, and also to suchstructures during various stages of integrated circuit fabrication. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the various embodiments is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

A NAND array architecture may be an array of memories (e.g., memorycells) arranged such that the memories of the array are coupled inlogical rows to access lines (conventionally referred to as word lines).Some memories of the array are coupled together in series between sourcelines and data lines (conventionally referred to as bit lines).

In some embodiments described herein, an etch stop of oxide (e.g.,aluminum oxide) may be applied on a source of polysilicon in a 3Dsemiconductor device.

In other embodiments described herein, an etch stop structure includinga first etch stop of nitride and a second etch stop of oxide (e.g.,aluminum oxide) may be applied on a source of Tungsten Silicide(hereinafter “WSiX”) in a 3D semiconductor device.

Therefore, monolithic channels may be achieved in 3D semiconductordevices with reduced interfaces, punches, and backfills inside thechannels such that relatively independent gate controls may be obtained.

In some embodiments described herein, different doping configurationsmay be applied to a select gate source (SGS), a control gate (CG) and aselect gate drain (SGD), each of which, in this example, may be formedof or at least include polysilicon; with the result such that thesetiers (e.g., including polysilicon) may have different etch rates whenexposed to an etching solution. For example, in a process of forming amonolithic pillar in a 3D semiconductor device, the SGS and the CG mayform recesses, while the SGD may remain less recessed or even notrecessed. These doping configurations may thus enable selective etchinginto the distinct tiers (e.g., SGS, CG, and SGD) in the 3D semiconductordevice by using an etching solution (e.g., tetramethylammonium hydroxide(TMCH)).

FIGS. 1A-1N are cross-sectional views illustrating an example method ofmaking a 3D semiconductor device, in which each figure illustrates arepresentative stage of forming the device according to an embodiment ofthe application.

Initially referring to FIG. 1A, a stack structure 100 is formed. In someembodiments, the stack structure 100 may include a source 101 ofpolysilicon, an etch stop 102 of oxide on the source 101, an SGS 103 ofpolysilicon on the etch stop 102, a first isolation oxide 104 on the SGS103, a CG 105 (e.g., including polysilicon) on the first isolation oxide104, a second isolation oxide 106 on the CG 105, and an SGD 107 of polyon the second isolation oxide 106.

In some embodiments, the stack 100 may further include a cap 108 ofnitride on the SGD 107. In some embodiments, the stack 100 may furtherinclude a hard mask 109 (e.g., of carbon) on the cap 108 of nitride.

Referring to FIG. 1B, an opening 110 is formed by etching to verticallyextend into the stack 100 to expose the source 101.

Referring to FIG. 1C, the opening 110 is laterally etched by using anetching solution (e.g., TMCH). Therefore, a first lateral recess 112 isformed into the SGS 103, and a second lateral recess 114 is formed intothe CG 105. In some embodiments, the first recess 112 is formed intoboth the SGS 103 and the etch stop 102. As will be explained in moredetail with reference to FIG. 3, doping configurations of the SGS 103,the CG 105, and the SGD 107 are different, and thus may lead toselective etchings into different tiers (e.g., the SGS 103, the CG 105,and the SGD 107) with different laterally recessed depths relative tothe dimension of the original opening 110. In some embodiments, a firstlateral depth of the first recess 112 into the SGS 103 is less than asecond lateral depth of the second recess 114 into the CG 105, while theSGD 107 remains least recessed, or even remains unrecessed. As isapparent, once the lateral etching is performed, the lateral depth ofthese recesses changes the width of the opening at the etched tiers.Therefore, the width of the opening 110 adjacent the SGS 103 is greaterthan the width of the opening 110 adjacent the SGD 107.

Referring to FIG. 1D, a dielectric 116 is deposited on a bottom surfaceand a side surface of the opening 110 (as well as on surfaces of thefirst recess 112 and the second recess 114), and can be seen as aninterpoly dielectric (IPD) structure 116. The IPD 116 may be formed asan “ONO” structure, including a first oxide 116A, a nitride 116B, and asecond oxide 116C, with the nitride 116B between the first oxide 116Aand the second oxide 116C.

Referring to FIG. 1E, a charge storage structure, is formed in thesecond recess 114. In the depicted example, the charge storage structureincludes a floating gate (FG) 120 including polysilicon formed in thesecond recess 114. In some embodiments, not shown in the drawings, theopening 110 (as well as the first recess 112 and the second recess 114)is first filled with polysilicon. Then, the polysilicon is removed fromthe opening 110 and the first recess 112, while the polysilicon remainsin the second recess 114. The remaining portion of the CG 105 mayfunction as a control gate. Therefore, the FG 120 is formed within thesecond recess 114, and is horizontally separated from the CG 105 by theIPO 116.

Referring to FIG. 1F, a gate oxide 122 is formed on a side surface ofthe FG 120 facing towards the opening 110 to function as a tunnel oxide.

In some embodiments, some portions of the IPD 116 are removed from theside surface and the bottom surface of the opening 110. In someembodiments, a large portion (e.g., the nitride 116B and the secondoxide 116C) of the IPD 116 is removed from the side of the opening 110,while a small portion (e.g., the second oxide 116C) of the IPD 116 isremoved from the bottom surface of the opening 110. Therefore, the firstoxide 116A of the IPD 116 may remain on the side surface of the opening110, and the first oxide 116A and the nitride 116B of the IPD 116 mayremain on the bottom surface of the opening 110.

Referring to FIG. 1G, a liner 130A of polysilicon is formed on thebottom surface and the side surface of the opening 110. In someembodiments, the liner 130A of polysilicon may be deposited on thebottom surface and the side surface of the opening 110.

Referring to FIG. 1H, the liner 130A of polysilicon and the IPD 116 onthe bottom surface of the opening 110 are removed (e.g., punched away)by a downward etching to expose the source 101, while the liner 103A ofpolysilicon on the side surface of the opening 110 remains. During thedownward etching process, the IPD 116 on the bottom surface of theopening 110 may function as a protection (e.g., an etch stop) to thesource 101.

Referring to FIG. 1I, a deposition 130B of polysilicon is formed on thetop surface of the source 101 by a downward deposition. Therefore, thedeposition 130B of polysilicon is in contact with the liner 130A ofpolysilicon that is deposited on the side surface of the opening 110. Anintegrated channel 130 (including both the liner 103A and the deposition130B) is thus formed to work with the source 101, the SGS 103, the FG120, and the SGD 107.

In some embodiments, the channel 130 contacts the source 101 at a lowerportion of the opening 110, and is laterally separated from the SGS 103,the FG 120, and the SGD 107 by oxides.

Referring to FIG. 1J, in some embodiments, the opening 110 is filledwith an oxide filler 140.

Referring to FIG. 1K, in some embodiments, the oxide filler 140 isremoved from an upper portion of the opening 110 to form a shallowrecess 110A, which extends from a top of the opening 110 to a leveladjacent to the SGD 107. Referring to FIG. 1L, a polysilicon filler 150can be filled into the shallow recess 110A (formed in the upper portionof the opening 110) to form a plug 150 of polysilicon.

Referring to FIG. 1M, in other embodiments, the oxide filler 140 isremoved from an upper portion of the opening 110 to form a deep recess110B, which extends from the top of the opening 110 to a level adjacentto the FG 120. Referring to FIG. 1N, a polysilicon filler 150 can befilled into the deep recess 110B (formed in the upper portion of theopening 110) to form a plug 150 of polysilicon.

Therefore, a semiconductor device 100, as illustrated above, may have anintegrated channel 130 without interfaces inside the channel. Thisprocess of making such a semiconductor device may provide relativelyindependent control of gates.

FIGS. 2A-2H are cross-sectional views illustrating an example method ofmaking a 3D semiconductor device, in which each figure illustrates arepresentative stage of forming the device, according to anotherembodiment of the application.

Initially referring to FIG. 2A, a stack structure 200 is formed. In someembodiments, the stack structure 200 may include a source 201 of WSiX, afirst etch stop 202A of nitride on the source 201, a second etch stop202B of oxide on the first etch stop 202A, a SGS 203 of polysilicon onthe second etch stop 202B, a first isolation oxide 204 on the SGS 203, aCG 205 of polysilicon on the first isolation oxide 204, a secondisolation oxide 206 on the CG 205, and a SGD 207 of polysilicon on thesecond isolation oxide 206.

In some embodiments, the stack 200 may further include a cap 208 ofnitride on the SGD 207. In some embodiments, the stack 100 may furtherinclude a hard mask 209 (e.g., of carbon) on the cap 208 of nitride.

Referring to FIG. 2B, an opening 210 is formed to vertically extend intothe stack 200 by etching to a level adjacent to the first etch stop 202Ato expose the first etch stop 202A.

Referring to FIG. 2C, the opening 210 is laterally etched by using anetching solution (e.g., TMCH) such that a first recess 212 is formedinto the SGS 203 and a second recess 214 is formed into the CG 205. Insome embodiments, a first lateral depth of the first recess 212 into theSGS 203 is less than a second lateral depth of the second recess 214into the CG 205, while the SGD 207 remains least recessed, or even notrecessed. Therefore, the width of the opening 210 adjacent the SGS 203is greater than the width of the opening 210 adjacent the SGD 207.

Referring to FIG. 2D, an interpoly dielectric (IPD) 216 is deposited ona bottom surface and a side surface of the opening 210 (as well as onsurfaces of the first recess 212 and the second recess 214). The IPD 216may include a first oxide 216A, a nitride 216B, and a second oxide 216C.The nitride 216B is between the first oxide 216A and the second oxide216C.

Referring to FIG. 2E, a FG 220 of polysilicon is formed in the secondrecess 214. In some embodiments, not shown in the drawings, the opening210 (as well as the first recess 212 and the second recess 214) is firstfilled with a polysilicon material. Then, the polysilicon material isremoved by etching from the opening 210 and the first recess 212, whilethe polysilicon material remains in the second recess 214. The firstetch stop 202A may function as an etch stop to protect the source 201 ofWSiX during the etching process. The remaining portion of the CG 205 mayfunction as a control gate. Therefore, the FG 220 is formed within thesecond recess 214, and is horizontally separated from the CG 205 by theIPO 216.

Referring to FIG. 2F, a gate oxide 222 is formed on a side surface ofthe FG 220 facing towards the opening 210. The gate oxide 222 mayfunction as a tunnel oxide.

Referring to FIG. 2G, a liner 230 of polysilicon is deposited on thebottom surface and the side surface of the opening 210 to function as anintegrated channel.

Referring to FIG. 2H, in some embodiments, the opening 210 is filledwith an oxide filler 240.

Similar to the embodiments of the semiconductor device 100 as shown inFIGS. 1L and 1N, a plug of polysilicon may be formed in an upper portionof the opening 210. In some embodiments, a plug of polysilicon mayextend from the top surface of the opening 210 to a shallow leveladjacent to the SGD 207. In other embodiments, the plug of polysiliconmay extend from the top surface of the opening 210 to a deep leveladjacent to the FG 220.

Therefore, a semiconductor device 200, as illustrated above, may have anintegrated channel 230 without interfaces inside the channel.

FIG. 3 is a flow chart illustrating a method of making a 3Dsemiconductor device according to an embodiment of the application.

In some embodiments, during a process of making a semiconductor device,among other things, different material configurations (such as dopingdifferences) may be employed within a stack of an SGS, a CG, and an SGDof polysilicon so as to obtain different etching rates for the tiers byusing an etching solution (e.g., TMAH). Therefore, a monolithic pillarmay be created in a semiconductor device, in which the SGS and the CG ofpolysilicon respectively form recesses, while the SGD of polysilicon isprevented from being etched, and thus is much less recessed, or evenunrecessed.

Referring to FIG. 3, at 302, a stack (e.g., 100) including an SGS (e.g.,103), a CG (e.g., 105), and an SGD (e.g., 107) of polysilicon is doped,in which the SGS is doped with a first doping configuration, the CG isdoped with a second doping configuration, and the SGD is doped with athird doping configuration.

At 304, an opening (e.g., 110) is formed by etching to vertically extendinto the stack.

At 306, the opening is laterally etched to form a first recess (e.g.,112) into the SGS, a second recess (e.g., 114) into the CG, and a thirdrecess (not shown) into the SGD. In some embodiments, TMAH may be usedto laterally etch the opening to form recesses into the SGS, the CG, andthe SGD.

Therefore, after the lateral etching process, a first depth of the firstrecess etched into the SGS relative to the original dimension of theopening (110) is less than a second depth of the second recess etchedinto the CG, while a third depth of the third recess etched into the SGDis much less than the first depth of the first recess etched into theSGS. In some embodiments, after the lateral etching process, the SGD mayremain unrecessed.

In some embodiments, at 302, the SGS (e.g., 103) of polysilicon is dopedwith boron at a doping concentration of about 1×2E20 cm⁻³ during adeposition of the SGS, the CG (e.g., 105) of polysilicon is doped withphosphorus at a doping concentration of about 1E21 cm⁻³ during a PlasmaEnhanced Chemical Vapor Deposition (PECVD) of the CG, and the SGD (e.g.,107) of polysilicon is doped with boron at a doping concentration ofabout 1E21 cm⁻³ in a diffusion furnace.

In some embodiments, at 302, the SGS of polysilicon is doped with boronat a doping concentration of about 1×2E20 cm⁻³ during a deposition ofthe SGS, the CG of polysilicon is doped with phosphorus at a dopingconcentration of about 1E21 cm⁻³ during a PECVD of the CG, and the SGDof polysilicon is doped with boron at a doping concentration of about2E20 cm⁻³ in a diffusion furnace.

In some embodiments, at 302, the SGS of polysilicon is doped with boronat a doping concentration of about 1×2E20 cm⁻³ during a deposition ofthe SGS, the CG of polysilicon is doped with phosphorus at a dopingconcentration of about 1E21 cm⁻³ during a PECVD of the CG, and the SGDof polysilicon is doped with carbon at a doping concentration of about1E16 cm⁻³.

In some embodiments, at 302, the SGS of polysilicon is doped with boronat a doping concentration of about 1×2E20 cm⁻³ during a deposition ofthe SGS, the CG of polysilicon is doped with phosphorus at a dopingconcentration of about 1E21 cm⁻³ during a Plasma Enhanced Chemical VaporDeposition (PECVD) of the CG, and the SGD of polysilicon is doped withboron at a doping concentration of about 2E20 cm⁻³ during a PECVD of theSGD.

In some embodiments, at 302, the SGS of polysilicon is doped with boronat a doping concentration of about 1×2E20 cm⁻³ during a deposition ofthe SGS, the CG of polysilicon is doped with phosphorus at a dopingconcentration of about 1E21 cm⁻³ during a PECVD of the CG, and the SGDof polysilicon is doped with about 1% to about 10% of N₂.

In some embodiments, at 302, the SGS of polysilicon is doped with boronat a doping concentration of about 1×2E20 cm⁻³ during a deposition ofthe SGS, the CG of polysilicon is doped with phosphorus at a dopingconcentration of about 1E21 cm⁻³ during a PECVD of the CG, and the SGDof polysilicon is doped with boron at a doping concentration of about2E20 cm⁻³ in a diffusion furnace.

In some embodiments, at 302, the SGS of polysilicon is doped with boronat a doping concentration of about 1×2E20 cm⁻³ during a deposition ofthe SGS, the CG of polysilicon is doped with phosphorus at a dopingconcentration of about 1E21 cm⁻³ during a PECVD of the CG, and the SGDof polysilicon is doped with NH₃.

In some embodiments, at 302, the SGS of polysilicon is doped boron at adoping concentration of about 1×2E20 cm⁻³ during a deposition of theSGS, the CG of polysilicon is doped with phosphorus at a dopingconcentration of about 1E21 cm⁻³ during a Plasma Enhanced Chemical VaporDeposition (PECVD) of the CG, and the SGD of polysilicon is doped withgermanium at a doping concentration of about 2E20 cm⁻³ using an ion beamimplant.

FIGS. 4A-4H are cross-sectional views illustrating an example method ofmaking a 3D semiconductor device, in which each figure illustrates arepresentative stage of forming the device, according to anotherembodiment of the application.

Initially referring to FIG. 4A, a stack structure 400 is formed. In someembodiments, the stack structure 400 may include a source 401 ofpolysilicon, an etch stop 402 of oxide on the source 401, an SGS 403 ofpolysilicon on the etch stop 402, a tier stack 406 including at leastone FG 420, and a tier of polysilicon 407 on the tier stack 406. In someembodiments, an opening 450 may vertically extend into the stack 400 toexpose the source 401. In some embodiments, the opening 450 may includea liner 430 of polysilicon. In some embodiments, the opening 450 may befilled with polysilicon.

Referring to FIG. 4B, in some embodiments, the stack 400 may furtherinclude a cap 408 of nitride on the tier of polysilicon 407.

Referring to FIG. 4C, in some embodiments, spacers 408A may be formed bydownward etching the cap 408 of nitride to expose the tier ofpolysilicon 407.

Referring to FIG. 4D, in some embodiments, a protection layer 460 may beformed over the surfaces of the opening 450, the spacers 408A, and thetier of polysilicon 407. In some embodiments, the protection layer 460may include multi-layer resist (MLR) material.

Referring to FIG. 4E, in some embodiments, the top surfaces of theopening 450 and the spacers 408A may be planarized with the protectionof the protection layer 460 of MLR.

Referring to FIG. 4F, in some embodiments, a mask 470 may be formed onthe planarized top surfaces of the opening 450 and the spacers 408A.

Referring to FIG. 4G, in some embodiments, with the mask 470 on theplanarized top surfaces of the opening 450 and the spacers 408A, theentire protection layer 460 of MLR and portions of the tier ofpolysilicon 407 may be selectively etched by downward etching.

Referring to FIG. 4H, in some embodiments, a filler 480 of oxide may befilled to cover the tier stack 406, the spacers 408A, the tier ofpolysilicon 407, and the opening 450.

While a number of embodiments are described herein, these are notintended to be exhaustive. Although specific embodiments have beenillustrated and described herein, it will be appreciated by those ofordinary skill in the art that any arrangement that is calculated toachieve the same purpose may be substituted for the specific embodimentshown. This application is intended to cover any adaptations orvariations of the disclosure. It is to be understood that the abovedescription is intended to be illustrative and not restrictive.Combinations of the above embodiments, and other embodiments, will beapparent to those of skill in the art upon studying the abovedescription.

The Abstract of the Disclosure is provided to comply with 37 C.F.R. § 1.72(b), requiring an abstract that allows the reader to quickly ascertainthe nature of the technical disclosure. It is submitted with theunderstanding that it will not be used to interpret or limit the claims.In addition, in the foregoing Detailed Description, it may be seen thatvarious features are grouped together in a single embodiment for thepurpose of streamlining the disclosure. This method of disclosure is notto be interpreted as limiting the claims. Thus, the following claims arehereby incorporated into the Detailed Description, with each claimstanding on its own as a separate embodiment.

1. A semiconductor device, comprising: a stack structure including, a source, a select gate source level over the source, a charge storage structure over the select gate source level, a select gate drain level over the charge storage structure, and an opening defined in the stack structure, the opening extending vertically into the stack structure to a level adjacent the source; and a channel material comprising polysilicon formed over a side surface and a bottom surface defining the opening, the channel material contacting the source at a lower portion of the opening, and being laterally separated from the charge storage structure by a tunnel dielectric, wherein a first width of the channel material adjacent the charge storage structure is substantially the same as a second width of the channel material adjacent the select gate drain level; and a conductive plug extending into the channel material from an upper surface of the channel material to a level lower than an upper surface of the select gate drain level.
 2. The semiconductor device of claim 1, wherein the charge storage structure is one of a plurality of charge storage structures in the stack structure, and wherein the second width of the opening adjacent the select gate drain level is substantially the same as a width of the opening adjacent the plurality of charge storage structures.
 3. The semiconductor device of claim 1, wherein the source comprises polysilicon.
 4. (canceled)
 5. The semiconductor device of claim 1, wherein the conductive plug extends from the upper surface of the channel material to a level adjacent a lower surface of the select gate drain level.
 6. The semiconductor device of claim 1, wherein the conductive plug extends from the upper surface of the channel material to a level adjacent the charge storage structure.
 7. The semiconductor device of claim 1, wherein the charge storage structure comprises a floating gate.
 8. A semiconductor device, comprising: a stack structure, the stack structure including, a source; an etch stop over the source, including, a first etch stop level including nitride over the source, and a second etch stop level including oxide over the first etch stop level, a select gate source level over the etch stop, a charge storage structure over the select gate source level, a select gate drain level over the charge storage structure, and an opening extending vertically into the stack structure to a level djacent the source; and a channel comprising polysilicon formed on a side surface and a bottom surface of the opening, the channel contacting the source at a lower portion of the opening, and being laterally separated from the charge storage structure by a tunnel dielectric, wherein a first width of the channel adjacent the select gate source level and the etch stop is greater than a second width of channel adjacent the select gate drain level.
 9. The semiconductor device of claim 8, wherein the stack structure further comprises a cap comprising nitride formed over the select gate drain level.
 10. The semiconductor device of claim 8, wherein the stack structure further comprises a control gate horizontally separated from the charge storage structure by an interpoly dielectric.
 11. The semiconductor device of claim 10, wherein the interpoly dielectric comprises a first oxide, a second oxide, and a nitride between the first oxide and the second oxide.
 12. The semiconductor device of claim 10, wherein the source comprises tungsten silicide, the select gate source level comprises polysilicon, the control gate comprises polysilicon, and the select gate drain level comprises polysilicon.
 13. A method of forming a semiconductor device, comprising: forming a stack structure, the stack structure including, a source, a select gate source level over the source, a plurality of control gate levels over the select gate source level, and a select gate drain level over the control gate level; forming an opening extending vertically into the stack structure the opening extending through the select gate drain level, the select gate source level and the plurality of control gate levels laterally etching the surfaces defining the opening to form a recess into the control gate level; forming an interpoly dielectric over a bottom surface and a side surface of the opening; forming a charge storage structure in the recess; and forming a channel comprising polysilicon on the bottom surface and the side surface of the opening, wherein a first width of the opening adjacent the charge storage structure is substantially the same as a second width of the opening adjacent the select gate drain level.
 14. The method of claim 13, further comprising a dielectric etch stop over the source, wherein the source comprises polysilicon.
 15. The method of claim 13, wherein forming the channel comprises: removing the interpoly dielectric from surfaces defining sides of the opening while leaving interpoly dielectric over at least a portion of the source underlying the opening; forming a liner comprising polysilicon on the bottom surface and the side surface of the opening; removing the bottom surface of the liner and the interpoly dielectric to expose the source; depositing polysilicon over the source sufficient to at least contact the liner on the side surface of the opening to form a continuous liner within the opening; and forming a filler comprising oxide within the continuous liner.
 16. The method of claim 13, further comprising: removing the filler from an upper portion of the opening to a level adjacent to the select gate drain; and forming a plug comprising polysilicon in the upper portion of the channel.
 17. The method of claim 13, further comprising: removing the filler from an upper portion of the opening to a level adjacent to the charge storage structure, and forming a plug comprising polysilicon in the upper portion of the channel.
 18. A method of forming a semiconductor device, comprising: forming a stack structure, the stack structure including, a source, a first etch stop level comprising nitride over the source, a second etch stop level comprising oxide over the first etch stop level, a select gate source level over the second etch stop level, a control gate level over the select gate source level, and a select gate drain level over the control gate level; forming an opening to extend vertically into the stack structure to expose the first etch stop level; laterally etching the opening to form a recess into the control gate level; forming an interpoly dielectric on a bottom surface and a side surface of the opening; forming a charge storage structure in the recess; and forming a channel on the bottom surface and the side surface of the opening, wherein a first width of the opening adjacent the charge storage structure is substantially the same as a second width of the opening adjacent the select gate drain level.
 19. The method of claim 18, wherein forming the channel comprises: removing the interpoly dielectric from a portion of the side surface of the opening, and removing the interpoly dielectric and the first etch stop level from the bottom surface of the opening to expose the source; forming a channel on the bottom surface and the side surface of the opening, wherein the channel is separated from the charge storage structure by a tunnel dielectric; and forming a filler comprising dielectric within the liner.
 20. The method of claim 18, further comprising: forming a plug comprising polysilicon in an upper portion of the opening to extend vertically from a top surface of the opening to a level adjacent to the select gate drain level.
 21. The method of claim 18, further comprising forming a plug comprising polysilicon in an upper portion of the opening to extend vertically from a top surface of the opening to a level adjacent to the charge storage structure.
 22. The method of claim 18, wherein forming the charge storage structure comprises: filling the opening with a polysilicon material; removing the polysilicon material from a portion of the opening, while leaving the polysilicon material in the recess to form the charge storage structure; and forming a gate oxide on a surface of the charge storage structure adjacent the opening.
 23. A method of forming a semiconductor device, comprising: forming a stack structure comprising a first select gate comprising polysilicon, a control gate comprising polysilicon over the first select gate, and a second select gate comprising polysilicon over the control gate, wherein the doping configurations of the first select gate, the control gate, and the second select gate are different; forming an opening through the stack structure to vertically extend into the stack; exposing the first select gate, the control gate, and the second select gate to an etching solution through the opening to form a recess in at least the polysilicon of the control gate; and forming a charge storage structure in the recess formed in the polysilicon of the control gate.
 24. The method of claim 23, wherein the etching solution used to form the recess comprises tetramethylammonium hydroxide (TMAH).
 25. The method of claim 23, wherein forming the stack structure comprises: doping the first select gate with boron at a doping concentration of about 1×2E20 cm⁻³ during deposition of the first select gate; doping the control gate with phosphorus at a doping concentration of about 1E21 cm⁻³ during Plasma Enhanced Chemical Vapor Deposition (PECVD) of the control gate; and doping the second select gate with boron at a doping concentration of about 1E21 cm⁻³.
 26. The method of claim 23, wherein forming the stack structure comprises: doping the first select gate level with boron at a doping concentration of about 1×2E20 cm⁻³ during deposition of the first select gate; doping the control gate with phosphorus at a doping concentration of about 1E21 cm⁻³ during PECVD of the control gate; and doping the second select gate with boron at a doping concentration of about 2E20 cm⁻³.
 27. The method of claim 23, wherein forming the stack structure comprises: doping the first select gate with boron at a doping concentration of about 1×2E20 cm⁻³ during a deposition of the first select gate; doping the control gate with phosphorus at a doping concentration of about 1E21 cm⁻³ during PECVD of the control gate; and doping the second select gate with carbon at a doping concentration of about 1E16 cm⁻³.
 28. The method of claim 23, wherein forming the stack structure comprises: doping the first select gate with boron at a doping concentration of about 1×2E20 cm⁻³ during deposition of the first select gate; doping the control gate with phosphorus at a doping concentration of about 1E21 cm⁻³ during PECVD of the control gate; and doping the second select gate with about 1% to about 10% of N₂.
 29. The method of claim 23, wherein forming the stack structure comprises: doping the first select gate with boron at a doping concentration of about 1×2E20 cm⁻³ during deposition of the first select gate source; doping the control gate with phosphorus at a doping concentration of about 1E21 cm⁻³ during PECVD of the control gate; and doping the second select gate with boron at a doping concentration of about 2E20 cm⁻³ in a diffusion furnace.
 30. The method of claim 23, wherein forming the stack structure comprises: doping the first select gate with boron at a doping concentration of about 1×2E20 cm⁻³ during deposition of the first select gate; doping the control gate with phosphorus at a doping concentration of about 1E21 cm⁻³ during PECVD of the control gate; and doping the second select gate with NH₃.
 31. The method of claim 23, wherein forming the stack structure comprises: doping the first select gate with boron at a doping concentration of about 1×2E20 cm⁻³ during deposition of the first select gate; doping the control gate with phosphorus at a doping concentration of about 1E21 cm⁻³ during PECVD of the control gate; and doping the second select gate with germanium at a doping concentration of about 2E20 cm⁻³ using an ion beam implant.
 32. The method of claim 23, wherein the polysilicon of the second select gate remains unrecessed after exposure to the etching solution. 